1. Field of the Invention
The present invention relates to an internal potential generation circuit mounted in a semiconductor integrated circuit device, and receiving an external power supply potential for generating an internal potential. More particularly, the present invention relates to an internal potential generation circuit that receives an external power supply potential for generating an internal potential required for writing and erasing data with respect to a nonvolatile memory device in a nonvolatile semiconductor memory device and the like.
2. Description of the Background Art
In a semiconductor integrated circuit device, particularly, in a non-volatile semiconductor memory device such as a flash memory, data is written through a tunnel current and the like to a memory cell transistor having a floating gate. It is therefore necessary to generate a voltage higher than the external power supply voltage (for example Vcc=3.3V) on the chip.
When a structure is implemented in which a sense amplifier is commonly shared by left and right bit line pairs such as in a dynamic semiconductor memory device (referred to as DRAM hereinafter) as well as in a nonvolatile semiconductor memory device, a boosted potential of a sufficient high level must be applied to the gate of the transistor for bit line isolation that opens/closes the connection between the sense amplifier and the left and right bit line pairs. If a boosted voltage is not applied, the potential level of the H level (logical high) data written into a memory cell will be reduced by the threshold voltage of the bit line isolation transistor even when the bit line isolation transistor is rendered conductive in a data writing operation to a memory cell or a data rewriting operation in a refresh operation mode.
For example, in a data output circuit, a great current flows to the output transistor. Therefore, an N channel MOS transistor is used to avoid CMOS latch up. In this case, reduction in the charging rate with respect to the load caused by a lower potential corresponding to the threshold voltage of the output transistor must be avoided. It is therefore necessary to drive the gate of the N channel MOS output transistor with a boosted potential.
In a nonvolatile semiconductor memory device such as a flash memory, a negative potential must be applied to the control gate, the source line, and the substrate according to the operation mode in a write operation and an erasure operation, as will be described afterwards.
In general, a negative potential is applied to the substrate side in order to improve the latch up resistance of the CMOS circuit and to suppress threshold value variation of the MOS transistor in a DRAM.
In this case, a negative potential must be generated from an externally applied single power supply potential (for example Vcc=3.3V).
In the above-described cases where an internal potential higher than the external power supply potential or a negative internal potential is to be generated, a charge pump circuit is generally employed.
FIG. 19 is a circuit diagram showing main components of a charge pump circuit 2000 for generating a positive internal high potential.
Charge pump circuit 2000 includes N channel MOS transistors Q1-Q7 connected in series between an output node N.sub.H from which a positive internal high potential is output and a power supply potential Vcc, each transistor being diode-connected, and capacitors C1-C6 having respective ends connected to the gates of transistors Q2-Q7. A clock signal PH is applied to the other ends of capacitors C1, C3 and C5. A clock signal /PH complementary (non-overlapping) to clock signal PH is applied to the other ends of capacitors C2, C4 and C6.
FIG. 20 is a schematic diagram showing a cross section of transistors Q1-Q7 of FIG. 19. A structure equal to a diode with the forward direction from the source to the drain is implemented since the gate electrode and the source are connected.
FIG. 21 shows an equivalent circuit of FIG. 19.
FIG. 22 is a timing chart showing the transition of clock signals PH and /PH over time.
The operation of charge pump circuit 2000 will be described briefly hereinafter with reference to FIGS. 21 and 22.
The potential of the node connected to signals PH and /PH via the capacitor varies in synchronization with these signals.
At time t1 in FIG. 22 when signal PH attains an H level (Vcc level) and signal /PH attains an L level (GND level), the potentials of nodes N1, N3 and N5 have to rise, and the potentials of nodes N2, N4 and N6 have to become lower in response to signals /PH.
However, there is a diode connected respectively between nodes N1 and N2, between nodes N3 and N4, and between nodes N5 and N6. Therefore, a forward current flows from node N1 to node N2 via diode Q2. Similarly, a forward current flows from node N3 to node N4 via diode Q4. Also, a forward current flows from node N5 to node N6 via diode Q6. The potentials of nodes N2, N4 and N6 do not exhibit a great reduction during the period of time t1-t2.
At time t2, signal PH is driven to an L level, and signal /PH is driven to an H level. Likewise the case of time t1-t2, the potential reduction of node N1 does not correspond to the reduction of signal PH due to the current flowing from power supply potential Vcc via diode Q1. Similarly, the potential reduction of nodes N3 and N5 is not so great as the reduction of signal PH due to the current flowing from nodes N2 and N4 via diodes Q3 and Q4, respectively.
By repeating the above operation, a potential of a level sufficiently higher than the level of internal power supply Vcc is output to output node Nh.
The diode of charge pump circuit 2000 of FIG. 19 is formed by the connection of the source and gate of a MOS transistor. Here, the potential difference of boosting is represented by the following equation. EQU (Amplitude of signal applied as a pulse-threshold value of MOS transistor).times.number of stages (1)
In a steady state, the supply current I.sub.OUT provided from charge pump circuit 2000 is represented by the following equation. EQU I.sub.OUT =f.times.(C+Cs).times.V.sub.t (2)
where f is the frequency of the clock signal supplied to the charge pump, C is the sum of the capacitance of coupling capacitors C1-C6, Cs is the parasitic capacitance, and V.sub.L is the voltage amplitude when the coupling capacitor is charged/discharged.
It is appreciated from equation (2) that a greater output current is provided in proportion to a larger sum C of the capacitance of coupling capacitors C1-C6.
In a transition state, the load capacitor can be charged more speedily with a greater output current.
The operation of a nonvolatile semiconductor memory device, for example a flash memory, that operates employing the above internal potential generation circuit will be described hereinafter.
FIGS. 23A and 23B are schematic sectional views of a floating gate type transistor forming the memory cell of a conventional nonvolatile semiconductor memory device. The former shows the case of a writing operation, and the latter shows the case of an erasure operation.
Referring to FIGS. 23A and 23B, a memory cell transistor includes an n type drain region 1502 and an n type source region 1504 formed at the surface of a p type semiconductor substrate 1500, a floating gate 1506 formed on a channel region between drain region 1502 and source region 1504 with a thin tunnel oxide film (for example, film thickness=10 nm) thereunder, and a control gate 1508 layered on floating gate 1506 with an insulation film thereunder.
A bit line BL is connected to drain region 1502. A predetermined potential is selectively applied to source region 1504 via a source line SL (not shown). Source region 1504 alternatively attains a floating state.
The conductance across the source and drain corresponds to the potential applied to the control gate. The channel conductance increases as the potential applied to the control gate becomes higher. More specifically, when the potential of the control gate is increased while a predetermined voltage is applied across the drain and source, the current Ids flowing across the source and drain will also increase.
The level of the control gate potential at which a current Ids begins to flow across the source and drain by increase of the potential of the control gate is called the cell threshold value.
This cell threshold value increases as electrons are accumulated at floating gate 1506 initially attaining an electrically neutral state.
In other words, current will not flow across the source and drain unless a higher voltage is applied to the control gate in proportion to a greater amount of electrons accumulated at floating gate 1506.
Since a floating gate is electrically cut off by an insulation film, information is stored in a nonvolatile manner by the accumulated electrons. The data written in a memory cell can be identified depending upon whether a current flows across the source and drain when a predetermined potential difference, for example each 1V is applied across the source and drain and a constant potential, for example 3V, is applied to control gate 1508.
FIG. 24 shows examples of potentials applied to bit line BL, control gate 1508, source line SL and substrate 1500 for respective cases of writing data into the above-described memory cell, erasing data, and reading out data.